Simple state
A simple state is an element of the state machine that does not have sub-states (it contains no regions or pseudostates). It is processed (enter action, do action) when it is reached by an incoming transition.
A simple state belongs to a region.
Symbol
A simple state is shown as a rectangle with rounded corners.
Symbol in context
Example 1
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'Simple state 1' is reached and becomes active (via the transition emanating from the initial pseudostate).
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Enter and do behaviors are executed in this order.
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When the transition leaving 'Simple state 1' is executed, the exit behavior of 'Simple state 1' is executed.
Example 2
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The 'Composite state 1' is entered and becomes active (via the transition emanating from the outer initial pseudostate).
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Its entry behavior is executed and then the transition emanating from the initial pseudostate within 'Composite State 1' is executed.
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'Simple state 1' is entered and becomes active . The enter and do behaviors are executed.
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When the transition leaving 'Simple state 1' becomes active, the exit behavior of 'Simple state 1' is executed when it is exited.
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Also 'Composite State 1' is exited (and its exit behavior is executed).
Characteristics
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A simple state can have entry, do, and exit behaviors.
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A simple state contains no regions.
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A simple state contains no pseudostates.
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A simple state can defer events.
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A simple state can store an error event that will be processed in case of an standard exception is raised when executing the 'do' behavior.
Interpretation of and deviation from the UML specification
There is no interpretation of and deviation from the UML specification for a state machine's simple state.